The present invention relates to electronic switches and, more particularly, to electronic switches for switched capacitor circuitry used in analog-to-digital converters.
A successive-approximation-register (SAR) analog-to-digital converter (ADC) selectively stores analog input energy in storage capacitors and then successively taps that energy to convert an analog input voltage into a representative digital output value.
FIG. 1 is a schematic circuit diagram of a portion of a conventional 3-bit SAR ADC 100 having four storage capacitors Cs0, Cs1, Cs2, and Cs3 having relative capacitance levels of Cu, Cu, 2Cu, and 4Cu, respectively. The SAR ADC 100 also has top-plate sampling switch STP, four bottom-plate sampling switches Sin0-Sin3, and eight bottom-plate conversion switches Sw10-Sw13 and Sw20-Sw23. Note that the top plates of the four storage capacitors Cs0-Cs3 are all shorted together at top-plate node TP, while each storage capacitor Csi has its own distinct bottom-plate node Bpi.
The switch STP selectively connects the top-plate node to a common-mode reference voltage Vcm, the switches Sin0-Sin3 selectively connect the corresponding bottom-plate nodes BP0-BP3 to the input voltage Vin, the switches Sw10-Sw13 selectively connect the corresponding bottom-plate nodes BP0-BP3 to a high reference voltage Vrh, and the switches Sw20-Sw23 selectively connect the corresponding bottom-plate nodes BP0-BP3 to a low reference voltage Vrl. In this specification, it will be assumed that Vrl is at ground (i.e., 0V), Vrh is at the supply voltage VDD, Vcm is at VDD/2, and Vin can be at any voltage level from 0V to VDD. Those skilled in the art will understand that other implementations may involve different voltage levels for one or more of these analog signals.
The SAR ADC 100 has two operational phases: a sampling phase during which the input voltage Vin is sampled and electrical energy (in the form of charge) is stored in the storage capacitors Cs0-Cs3 and a conversion phase during which the stored energy in each of the storage capacitors Cs0-Cs3 is successively evaluated to generate the representative digital output value.
During the sampling phase, the sampling switches STP and Sin0-Sin3 are closed and the conversion switches Sw10-Sw13 and Sw20-Sw23 are open. As such, during the sampling phase, the top-plate node TP is driven to Vcm through the switch STP and the bottom-plate nodes BP0-BP3 are all driven to Vin through the switches Sin0-Sin3.
At the end of the sampling phase, the sampling switches STP and Sin0-Sin3 are all open, thereby (ideally) “freezing” the amount of energy (i.e., charge) stored in each of the storage capacitors Cs0-Cs3. As such, the voltage stored across each of the storage capacitors Cs0-Cs3 will (ideally) be fixed at the difference (Vcm-Vin) between the common-mode reference voltage Vcm and the input voltage Vin.
During the conversion phase, with the sampling switches STP and Sin0-Sin3 open, the conversion switches Sw10-Sw13 and Sw20-Sw23 are controlled to successively evaluate the energy stored in each of the storage capacitors Cs0-Cs3. During the conversion phase, depending on the voltage level of Vin during the sampling phase, the top-plate node TP will be driven somewhere between 0V and VDD. For example, when Vin=VDD, the node TP will be driven to 0V during the conversion phase; when Vin=VDD/2, the node TP will be driven to VDD/2 during the conversion phase; and, when Vin=0V, the node TP will be driven to VDD during the conversion phase.
It is known to implement the top-plate sampling switch STP using an n-type MOSFET (metal-oxide semiconductor, field-effect transistor) device, a p-type MOSFET device, or a transmission gate having an n-type MOSFET device and a p-type MOSFET device connected in parallel.
FIG. 2 is a schematic diagram of a conventional four-terminal, n-type MOSFET device 200 having a gate terminal G, a source terminal S, a drain terminal D, and a body (or bulk) terminal B. As indicated in FIG. 2, there is an inherent diode relationship between the drain terminal D and the body terminal B that ideally prevents current from flowing from the drain terminal D to the body terminal B. Similarly, there is an inherent diode relationship between the source terminal S and the body terminal B that ideally prevents current from flowing from the source terminal S to the body terminal B.
Nevertheless, when an actual device 200 is biased in the off/accumulation region, significant drain-to-body leakage current (a.k.a. GIDL) and significant source-to-body leakage current (a.k.a. GISL) can be observed, even for drain/source biases much lower than the device's breakdown voltage. The GIDL leakage current has a strong dependence on the drain-to-body voltage VDB and the drain-to-gate bias voltage VDG. As VDB and/or VDG increases, the GIDL leakage current increases exponentially. Similarly, the GISL leakage current has a strong dependence on the source-to-body voltage VSB and the source-to-gate bias voltage VSG. As VSB and/or VSG increases, the GISL leakage current increases exponentially.
Note that p-type MOSFET devices are also susceptible to GIDL and GISL leakage currents. For n-type devices, the GIDL leakage current is highest when the drain voltage reaches the highest voltage (i.e., VDD), and the GISL leakage current is highest when the source voltage reaches the highest voltage. For p-type devices, on the other hand, the GIDL leakage current is highest when the drain voltage reaches the lowest voltage (i.e., ground or zero volts), and the GISL current is highest when the source voltage reaches the lowest voltage. Note that, a transmission gate having both an n-type device and a p-type device will exhibit high GIDL/GISL leakage currents at both full-scale voltage and at zero voltage.
When the top-plate sampling switch STP of FIG. 1 is implemented using an n-type MOSFET device, like the device 200 of FIG. 2, the device's drain terminal D is connected to the reference voltage Vcm, the device's body terminal B is connect to ground, the device's source terminal S is connected to the top-plate node TP, and the device's gate terminal G is connected to control circuitry (not shown in FIG. 1) that turns on the device 200 (i.e., closes the switch STP) and turns off the device 200 (i.e., opens the switch STP).
During the conversion phase with the switch STP open, the top plate TP of the storage capacitor Cs is undriven. If there is any charge leakage, such as the charge leakage associated with GIDL and/or GISL leakage current, through the open switch STP, then the energy stored in the storage capacitors Cs0-Cs3 will change, which can adversely affect the accuracy of the digital output value generated by the ADC.
It would be advantageous to provide switch circuitry for the top-plate sampling switch STP of FIG. 1 that has reduced leakage current.